Semiconductor structures and manufacturing methods

ABSTRACT

A method of making a semiconductor device includes forming an alignment mark in a semiconductor wafer. The alignment mark includes a fist set of parallel lines and a second set of parallel lines. The parallel lines in the first set overlie and cross the parallel lines in the second set. The alignment mark can be used to determine a location of the semiconductor wafer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.09/733,665, filed on Dec. 8, 2000, which is divisional of the U.S.patent application Ser. No. 09/362,976, filed on Jul. 28, 1999, nowabandoned, which applications are hereby incorporated herein byreference.

TECHNICAL FIELD

This invention relates generally to semiconductor structures andmanufacturing methods and more particularly to alignment techniques usedtherein.

BACKGROUND

As is known in the art, semiconductor integrated circuits aremanufactured using a series of process steps that require properalignment of the semiconductor wafer. Many alignment systems usereflected light from profile patterns formed on the surface of thesemiconductor wafer to determine the location of the wafer. Such anarrangement is shown in FIG. 1. An alignment illumination 10, here across, is focused onto the surface 12 of the semiconductor wafer 14using an optical system 16. A portion of the light reflected from thesurface of the semiconductor wafer is directed by the optical system 16to a detector arrangement 20. The wafer 14 has formed along one portionthereof an alignment mark 22, here shown diagrammatically as a series ofgrooves 24 etched into the surface 12 of the wafer 14. As the wafer 14is scanned horizontally, the detector arrangement 20 produces waveforms,which enable detection of the alignment of the wafer 14 relative to theoptical system 16.

More particularly, and referring also to FIG. 2, there are shown foursites, i.e., site 1, site 2, site 3 and site 4, of alignment marks oneach of both the upper and lower peripheral portions of a semiconductorwafer 14. Each one of the sites includes two sets of lines 13, one at+45 degrees with respect to the vertical, or Y axis, and the other setof lines 15 being at −45 degrees with respect to the Y axis. Thealignment illumination projected by the optical system (FIG. 1) onto thesurface of the wafer is a cross, such as used in the MICRASCAN equipmentmanufactured by Silicon Valley Group (SVG), San Jose, Calif. A“standard” alignment mark, in one half of a site, for the MICRASCAN IIIequipment is shown in FIG. 3 and consists of wide stripes at a 45 degreeangle separated by variable spacing. Another version is shown in FIG. 4and is made up of lines at the locations where the “standard” mark hasthe edges of its stripes. The size of both versions is 60×60micrometers. The alignment marks etched into the surface of the waferare shown in FIG. 2 as a pair orthogonal sets of a series of parallellines, only one of the two sets being shown in FIGS. 3 and 4.

Referring again to FIG. 1, the alignment illumination is a cross that isprojected onto the surface 12 of wafer 14 with the pair of intersectingarms of the cross being disposed nominally orthogonal to the lines ineach of the sites. The cross-shaped light (i.e., the alignmentillumination) is projected by the optical system 16 onto, and scannedacross, the site (FIG. 2) along the X direction indicated on the surface12 of the wafer 14. The optical system 16 includes a prism (FIG. 1) thatdirects a portion of the light reflected surface 12 of the wafer 14 ontoa detector arrangement 20 shown diagrammatically in FIG. 1. Thus, asindicated, there are four detectors 22 ₁, 22 ₂, 22 ₃, and 22₄; one pair22 ₁ and 22₂ being disposed along an axis +45 degrees with respect tothe Y axis and one pair 22 ₃ and 22₄ being disposed along an axis −45degrees with respect to the Y axis. The pair of detectors 22 ₁ (i.e.,“Left +45”) and 22 ₂ (i.e., “Right +45”) is used for detection of lightreflected by lines 13 at +45 degrees with respect to the Y axis and thepair of detectors 222 ₃ (i.e., “Left −45”) and 22 ₄ (i.e., “Right −45”)are used to detect light reflected by lines 15 at −45 degrees withrespect to the Y axis.

More particularly, to determine the location of an alignment site, twomarks 13, 15 (FIG. 2), one oriented at +45 degrees and one at −45degrees with respect to the Y axis, are required. The alignment marks13, 15 are scanned by the optical system with an X shaped illumination,as described above. The light reflected from the surface of the waferand the alignment lines is detected in the dark field mode, i.e., onlylight scattered from the marks at an angle is analyzed. Two detectors 22₁ and 22 ₂ record simultaneously the reflected light; one detector 22 ₂located to the right side and one detector 22 ₁ to the left side of themark's edge. When scanning the +45 degree lines 13, the set of detectors22 ₁ and 22 ₂ is activated and when the −45 degree lines 15 are scanned,the set of detectors 22 ₃, 22 ₄ are activated. More particularly,referring to FIG. 1, when the alignment illumination is over the +45degree lines 13 of site 1, the “Left +45” and “Right +45” detectors 22 ₁and 22 ₂ are activated and the “Left −45” and “Right −45” detectors 22 ₃and 22 ₄, are deactivated. When the alignment illumination moves overthe −45 degree lines 15 of site 1, the “Left −45” and “Right −45”detectors 22 ₃ and 22 ₄ are activated and the “Left +45” and “Right +45”detectors 22 ₁ and 22 ₂ are deactivated. It is noted that with such anarrangement, each alignment site is made up of a pair of spatiallyseparated sets 13, 15 of parallel orthogonal lines with two sets in thesite being sequentially activated/deactivated detectors. Such spatialseparation increases the area required for an alignment site.

SUMMARY OF THE INVENTION

In accordance with the present invention, a semiconductor body isprovided having an alignment mark comprising a pair of sets of parallellines disposed on the semiconductor body. The parallel lines in one ofthe sets are disposed orthogonal to the parallel lines in the other oneof the set. The two sets of parallel lines are in an overlayingrelationship.

With such structure, the same amount of wafer surface area enables twiceas many alignment sites. Thus, the arrangement allows the alignmentsystem to acquire twice the amount of metrology information during thesame alignment scanning process to thereby increase the alignmentquality. Further, there is no loss of through-put because the same timeis used for scanning the sites as in the system described above.

In accordance with another embodiment, a method is provided fordetecting an alignment mark on a semiconductor body. The method includesproviding the alignment mark on the semiconductor body. This alignmentmark includes a pair of sets of parallel lines disposed on thesemiconductor body. The parallel lines in one of the sets are disposedorthogonal to the parallel lines in the other one of the set and the twosets of parallel lines are in an overlaying relationship. The alignmentillumination includes a pair of orthogonal, lines of impinging lightthat is scanned over the surface of the alignment mark. One of such pairof impinging light lines is orthogonal to, and laterally displaced from,the other one of such pair of impinging light lines. Impinging light isreflected by the alignment lines in the surface of the semiconductorwhen such impinging light is over to provide a pair of laterallydisplaced beams of reflected light. The method includes detecting ineach one of a pair of laterally spaced detectors a corresponding one ofthe laterally displaced beams of reflected light.

In accordance with another embodiment of the invention an apparatus isprovided for detecting an alignment mark on a semiconductor body. Thealignment mark comprises a pair of sets of parallel lines disposed onthe semiconductor body. The parallel lines in one of the sets aredisposed orthogonal to the parallel lines in the other one of the setand the two sets of parallel lines are in an overlaying relationship.The apparatus includes an optical system for scanning an alignmentillumination that provides a pair of orthogonal, lines of impinginglight over the surface of the alignment mark. One of such pair ofimpinging light lines is orthogonal to, and laterally displaced from,the other one of such pair of impinging light lines. Impinging light isreflected by the alignment lines in the surface of the semiconductorwhen such impinging light is over to provide a pair of laterallydisplaced beams of reflected light. The apparatus also includes a pairof laterally spaced detectors, each being positioned to detect acorresponding one of the laterally displaced beams of reflected light.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will become more readilyapparent from the following detailed description when read together withthe accompanying drawings, in which:

FIG. 1 is schematic diagram of an alignment system according to theprior art;

FIG. 2 is a plan view of a semiconductor wafer having alignment marksaccording to the prior art etched into such surface;

FIGS. 3 and 4 are sketches of alignment marks according to the priorart;

FIG. 5 is a plan view of a semiconductor wafer having alignment marksaccording to the invention etched into such surface;

FIGS. 6 and 7 are sketches of alignment marks according to theinvention; and

FIG. 8 is schematic diagram of an alignment system according to theinvention, such system being adapted for use with a semiconductor waferhaving the alignment marks shown in either FIG. 6 or FIG. 7.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Referring now to FIG. 5, a portion of a semiconductor body 100, here asingle crystal silicon body, is shown. The body includes alignmentsites. In particular, five sites (i.e., site 1, site 2, site 3, site 4and site 5) are disposed along the top outer peripheral portion of thewafer and five sites (i.e., site 1, site 2, site 3, site 4, and site 5)along the lower outer peripheral portion. Each one of the sites isidentical, an exemplary one thereof being shown in detail in FIG. 6.Another embodiment of one of the sites is shown in FIG. 7. It is notedthat the alignment site includes a single, composite alignment mark 102.The alignment mark 102, as noted above, is formed in a portion of thesurface 104 of the semiconductor body 102, here as grooves 106. Thesurface 104 of the semiconductor body 102 is adapted to reflect lightenergy impinging on such surface with a predetermined wavelength.

More particularly, the semiconductor body 100 has an alignment mark 102comprising a pair of sets of parallel lines 112, 114 (FIG. 6 or 7)disposed on the semiconductor body 100. The parallel lines 112 in one ofthe sets are disposed orthogonal to the parallel lines 114 in the otherone of the set and the two sets of parallel lines 112, 114 are in anoverlaying relationship to provide a composite mark at each one of thesites (FIG. 5).

An apparatus 200 shown in FIG. 8, is provided for detecting thealignment mark 102 (FIG. 6) on a semiconductor body 110. As noted above,the alignment mark 100 comprises a pair of sets of parallel lines 112,114 (FIG. 6) disposed on the semiconductor body 100. The parallel lines112, 114 in one of the sets are disposed orthogonal to the parallellines 112, 114 in the other one of the sets. The alignment mark 102includes, as noted above, grooves 106 having sidewalls 108 terminatingat the surface 104 of the semiconductor body 100, as indicated in FIG.8. The grooves 106 have bottom portions 110 recessed into the surfaceportion of the semiconductor body 100. The two sets of parallel lines112, 114 are in an overlaying relationship.

The apparatus 200 includes an optical system 202 for scanning analignment illumination 204, which comprises a pair of orthogonal,laterally displaced along the X axis lines 208, 210 of impinging lightover the surface of the alignment mark 102. One of the pair of impinginglight lines, here line 208, is orthogonal to, and laterally displacedfrom, the other one of such pair of impinging light lines 210. Here, theline 210 is projected onto the surface of the wafer 100 at an angle of−45 degrees with respect to the Y axis (FIG. 5) and the line 208 isprojected onto the surface of the wafer 100 at an angle of +45 degreeswith respect to the Y axis (FIG. 5). The impinging light (i.e., thealignment illumination) is reflected by the surface of the semiconductorbody 100 when such impinging light is over the composite alignment mark102 to provide a corresponding pair of laterally displaced beams 211,213 of reflected light.

The apparatus includes a detector arrangement 220. The detectorarrangement 220 includes a pair of detectors configurations 220 ₁ and220 ₂. The projected beams 211, 213 are directed by the optical system200 to the detector configurations 220 ₁ and 220 ₂, respectively, asindicated. The detector configuration 220 ₁ includes a pair of detectors222 ₁ and 222 ₂, shown in FIG. 8. Shown diagrammatically with thedetectors 222 ₁ and 222 ₂ is the projection of the illumination 210(i.e., 210′) if the surface of the wafer 100 were perfectly flat. Thus,detectors 222 ₁ and 222 ₂ are positioned to detect energy reflected bylines 112 (FIG. 6).

In like manner, the detector configuration 220 ₂ includes a pair ofdetectors 222 ₃ and 222 ₄, shown in FIG. 8. Shown diagrammatically withthe detectors 222 ₃ and 222 ₄ is the projection of the illumination 208(i.e., 208′) if the surface of the wafer 100 were perfectly flat. Thus,detectors 222 ₃ and 222 ₄ are positioned to detect energy reflected bylines 114 (FIG. 6).

With such apparatus, the alignment illumination is scanned over thesurface of the alignment mark 102. One pair of impinging light lines 108is orthogonal to, and laterally displaced from, the other one of suchpair of impinging light lines 110. Impinging light is reflected by thealignment lines in the surface of the semiconductor when such impinginglight is over to provide a pair of laterally displaced beams 211, 213lines of reflected light. The detectors 222 ₁, 222 ₂, 222 ₃ and 222 ₄detect in each one of a pair of laterally spaced detector configurations220 ₁, 220 ₂, respectively, a corresponding one of the laterallydisplaced beams 211, 213 of reflected light. The −45 degree and +45degree oriented alignment lines 208, 210, respectively, of thecross-shaped alignment illumination 204 are separated locally by atleast the width W (FIGS. 6 and 8) of the alignment mark 102. This willresult in the alignment mark being scanned first by the +45 degree line208 and subsequently by the −45 degree line 210. This arrangement allowsthe separation of the alignment detectors 222 ₁, 222 ₂ and 222 ₃, 222 ₄for +45 degree and −45 degree orientations, respectively. As a result,each signal, or waveform, produced by the detectors can be recordedwithout background noise from the other line orientation.

Other embodiments are within the spirit and scope of the appendedclaims. For example, other types of composite alignment marks may beused such as shown in FIG. 7.

1. A method of making a semiconductor device, the method comprising:providing a semiconductor wafer; and forming an alignment mark in thesemiconductor wafer, the alignment mark comprising a first set ofparallel lines and a second set of parallel lines, the parallel lines inthe first set overlying and crossing the parallel lines in the secondset.
 2. The method of claim 1 wherein the parallel lines in the firstset are aligned orthogonally relative to the parallel lines in thesecond set.
 3. The method of claim 1 wherein both the first set and thesecond set of parallel lines includes more than, three parallel lines.4. The method of claim 1 and further comprising using the alignment markto determine a location of the semiconductor wafer.
 5. The method ofclaim 4 wherein using the alignment mark to determine a location of thesemiconductor wafer comprises reflecting energy with a predeterminedwavelength from a surface of the semiconductor wafer.
 6. The method ofclaim 4 wherein using the alignment mark to determine a location of thesemiconductor wafer comprises: simultaneously directing a first beam oflight and a second beam of light toward the semiconductor wafer, thefirst beam of light being spaced from the second beam of light;receiving the first beam of light after the first beam of light has beenreflected from the semiconductor wafer; and receiving the second beam oflight after the second beam of light has been reflected from thesemiconductor wafer.
 7. The method of claim 6 wherein the first beam oflight comprises a first line of light and wherein the second beam oflight comprises a second line of light, the first line of light beingorthogonal to the second light of line.
 8. The method of claim 7 whereinthe parallel lines in the first set are aligned orthogonally relative tothe parallel lines in the second set.
 9. The method of claim 6 whereinthe first beam of light is received at a first detector and the secondbeam of light is received at a second detector.
 10. The method of claim1 wherein the semiconductor wafer comprises a semiconductor body ofsingle crystal silicon, and wherein forming an alignment mark comprisesetching grooves into the semiconductor body.
 11. The method of claim 1wherein forming an alignment mark comprises forming a plurality ofalignment marks.
 12. The method of claim 11 wherein the plurality ofalignment marks are formed along a line, the method further comprisingsimultaneously directing a first beam of light and a second beam oflight toward the semiconductor wafer, the first beam of light beingspaced from the second beam of light.
 13. A method of making asemiconductor device, the method comprising: providing a semiconductorwafer; and forming an alignment mark in the semiconductor wafer, thealignment mark comprising a first set of parallel lines and a second setof parallel lines, the parallel lines in the first set overlying andcrossing the parallel lines in the second set; using the alignment markto align the semiconductor wafer; and performing a process step to forman integrated circuit in the semiconductor wafer.
 14. The method ofclaim 13 wherein the parallel lines in the first set are alignedorthogonally relative to the parallel lines in the second set.
 15. Themethod of claim 13 and further comprising using the alignment mark todetermine a location of the semiconductor wafer.
 16. The method of claim15 wherein using the alignment mark to determine a location of thesemiconductor wafer comprises reflecting energy with a predeterminedwavelength from a surface of the semiconductor wafer.
 17. The method ofclaim 15 wherein using the alignment mark to determine a location of thesemiconductor wafer comprises: simultaneously directing a first beam oflight and a second beam of light toward the semiconductor wafer, thefirst beam of light being spaced from the second beam of light;receiving the first beam of light after the first beam of light has beenreflected from the semiconductor wafer; and receiving the second beam oflight after the second beam of light has been reflected from thesemiconductor wafer.
 18. The method of claim 17 wherein the first beamof light comprises a first line of light and wherein the second beam oflight comprises a second line of light, the first line of light beingorthogonal to the second line of light.
 19. The method of claim 13wherein the semiconductor wafer comprises a semiconductor body of singlecrystal silicon, and wherein forming an alignment mark comprises etchinggrooves into the semiconductor body.
 20. The method of claim 19 whereinforming an alignment mark comprises forming a plurality of alignmentmarks, each of the alignment marks comprising a first set of parallelgrooves and a second set of parallel grooves, the parallel grooves inthe first set overlying and crossing the parallel grooves in the secondset.